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E2C0028-27-Y4
Semiconductor MSC7110-01/7112-01
Semiconductor
This version: Nov. 1997 MSC7110-01/7112-01 Previous version: Jul. 1996
12-Segment 16-Digit or 16-Segment 12-Digit Display Controller/Driver
GENERAL DESCRIPTION
The MSC7110-01/MSC7112-01 is a display controller to display the timer of video tape recorder, channel operation, and other infomaiton by a vaccum fluorescent display tube. Display data is input by serial transfer from microcontroller.
FEATURES
* Provides the interface with a microcontroller by three signal lines. : DATA IN, CLOCK, and LOAD * Driver output can directly be connected to a vaccum fluorescent display tube without a pull-down resistor. * Display is turned on by dynamic drive mode. * The number of display digits are programmable in the range of : 1 to 12 digits (MSC7112-01) 1 to 16 digits (MSC7110-01) * 12-segment driver output : 16 driver outputs (MSC7112-01) 12 driver outputs (MSC7110-01) * The LED drivers can turn on 5 outputs statically. * RAM data can directly be displayed. * The brightness adjustment is programmable and brightness can be adjusted every 1/15 step. * Built-in power-on-reset circuit * The vacuum fluorescent display tube driver outputs high withstand voltage : VDD-VEE=45V (max). * Logic supply voltage : VDD=5V 10% * Package options: 42-pin plastic SDIP (SDIP42-P-600-1.78) : (Product name : MSC7110-01SS/MSC7112-01SS) 44-pin plastic QFP (QFP44-P-910-0.80-K) : (Product name : MSC7110-01GS-K/MSC7112-01GS-K) 44-pin plastic QFP (QFP44-P-910-0.80-2K) : (Product name : MSC7110-01GS-2K/MSC7112-01GS-2K)
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Semiconductor
BLOCK DIAGRAM
SCLK DATA IN LOAD I 18-bit S*R 18 POR bit 18 b 0-16 17 RAM 17 16W 17bits A0-A3 TEST MODE fW RAM PC L
RAM fR
LATCH
LATCH
SEG DRV SEG A (b0)
L 18-bit LATCH bit 0 LOAD 3 b15-17
(ROM) 17 PLA Address 32 16bits 16 Q 12 12
COMMAND DECODER 4
1
L PLA fR
OE DIGIT DRV
SEG L
(b11)
PLA PC1 CONTROL W/R 4 b0-3 4
TIMING GENERATOR
PC2 DECODER
ADDRESS SELECTOR
D1 LATCH 4 4 L
DIGIT LOAD BLANK
(0)
MSC7110-01
4 R*A*C R A=B R*A*C COUNT
D*R LATCH ADDRESS COMP
OSCI OSCO
OSC
W*A LOAD W*A*C COUNT 4 D*C*R LOAD b0-3
L
4
O
16
16
W*A*C
OE
D16
(15)
POR
L D*C*R
4 b0-3 L D*R LOAD DUTY CYCLE COUNTER
4 16 O
AB A=B A=B b0-4
4
POR
POR
4 D*C*C L DOWN COUNTER
BLANK DUTY L*R LATCH 5 L L*R LOAD 5
LED DRV LED1 5 LED5
MSC7110-01/7112-01
VDD (+5V) VSS (0V) VEE (-20 to -40) D*T*C S
DIGIT TIME COUNTER
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Semiconductor
SCLK DATA IN LOAD I 18-bit S*R 18 POR bit 18 COMMAND DECODER 3 b15-17 4 1 A0-A3 TEST MODE fW RAM PC L RAM fR PLA PC1 PC2 DECODER CONTROL W/R 4 b0-3 4
TIMING GENERATOR
LATCH b0-16 17
LATCH
SEG DRV SEG A (b0)
L 18-bit LATCH R bit 0 LOAD
RAM 17 16W 17bits 17
(ROM) PLA 16 Q 16 16
32 16bits
L PLA fR
OE DIGIT DRV
SEG P
(b15)
ADDRESS SELECTOR
D1 LATCH 4 4 L DIGIT LOAD BLANK BLANK DUTY L*R LATCH 5 L L*R LOAD 5 LED5 OE D12 4 O 12
(0)
MSC7112-01
4 R*A*C R A=B
ADDRESS COMP
OSCI OSCO
OSC
W*A*C LOAD W*A*C COUNT 4 D*C*R COAD b0-3
L
12
W*A*C
R*A*C COUNT D*R LATCH
R
(11)
POR
L D*C*R D*C*C L b0-3
4 L D*R LOAD DUTY CYCLE COUNTER
4 16 O
AB A=B A=B b0-4
4
LED DRV LED1 5
POR
POR
MSC7110-01/7112-01
DOWN COUNTER VDD (+5V) VSS (0V) VEE (-20 to -40) D*T*C S
DIGIT TIME COUNTER
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Semiconductor
MSC7110-01/7112-01
INPUT AND OUTPUT CONFIGURATION
Input Pin
VDD LOAD DATA IN SCLK OSCI VDD VDD R POR
Output Pin
VDD
OSCO VDD VDD
*1 SEGA-L *2 SEGA-P VEE VDD
LED1LED5
*2 D1-D12 *1 D1-D16 VEE
*1 MSC7110-01 *2 MSC7112-01 4/18
Semiconductor
MSC7110-01/7112-01
PIN CONFIGURATION (TOP VIEW)
MSC7110-01
OSCI 1 OSCO 2 POR 3 VDD 4 D1 5 D2 6 D3 7 D4 8 D5 9 D 6 10 D 7 11 D 8 12 D 9 13 D10 14 D11 15 D12 16 D13 17 D14 18 D15 19 D16 20 LED5 21 42 LOAD 41 DATA IN 40 SCLK 39 SEG A 38 SEG B 37 SEG C 36 SEG D 35 SEG E 34 SEG F 33 SEG G 32 SEG H 31 SEG I 30 SEG J 29 SEG K 28 SEG L 27 LED 1 26 LED 2 25 LED 3 24 LED 4 23 VEE 22 VSS
42-Pin Plastic SDIP Note: The product name actually printed on the product is "C7110-01".
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Semiconductor MSC7112-01
OSCI 1 OSCO 2 POR 3 VDD 4 D1 5 D2 6 D3 7 D4 8 D5 9 D6 10 D7 11 D8 12 D9 13 D10 14 D11 15 D12 16 LED1 17 LED2 18 LED3 19 LED4 20 LED5 21 42 LOAD 41 DATA IN 40 SCLK 39 SEG A 38 SEG B 37 SEG C 36 SEG D 35 SEG E 34 SEG F 33 SEG G 32 SEG H 31 SEG I 30 SEG J 29 SEG K 28 SEG L 27 SEG M 26 SEG N 25 SEG O 24 SEG P 23 VEE 22 VSS
MSC7110-01/7112-01
42-Pin Plastic SDIP Note: The product name actually printed on the product is "C7112-01".
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Semiconductor
D12 D13 D14 D15 D16 LED5 VSS VEE LED4 LED3 LED2
1 2 3 4 5 6 7 8 9
10 11

44 D11 43 D10 39 VEE 42 D9 41 D8 40 D7 LED1 12 SEGL 13 SEGK 14 15 16 VEE 17 SEGJ 44 D11 43 D10 SEGI 39 VEE 42 D9 41 D8 40 D7 SEGM 12 SEGL 13 SEGK 14 15 16 VEE 17 SEGJ SEGI
MSC7110-01/7112-01
MSC7110-01
38 D6 37 D5 36 D4 35 D3 34 D2
33 D1 32 VDD 31 POR 30 OSCO 29 OSCI 28 LOAD 27 DATA IN 26 SCLK 25 SEGA 24 SEGB 23 SEGC
SEGG 19 SEGF 20 36 D4 SEGE 21 35 D3 SEGD 22 34 D2
44-Pin Plastic QFP MSC7112-01
38 D6
SEGH 18
D12 LED1 LED2 LED3 LED4 LED5 VSS VEE SEGP SEGO SEGN
1 2 3 4 5 6 7 8 9
10 11

37 D5
33 32 31 30 29 28 27 26 25 24 23 SEGG 19 SEGF 20 SEGE 21 SEGD 22
D1 VDD POR OSCO OSCI LOAD DATA IN SCLK SEGA SEGB SEGC
44-Pin Plastic QFP 7/18
SEGH 18
Semiconductor
MSC7110-01/7112-01
PIN DESCRIPTION
Number of Pins 1 1 1 1 1 1 Connected to
Symbol VDD VSS VEE DATA IN SCLK LOAD
Type -- -- -- I I I
Description
Power source VDD-VSS: Supply voltage for internal logic VDD-VEE: Supply voltage for VF display tube driving circuit logic Microcontroller Input of display data of the shift register Input from the MSB (positive logic). Shift clock of the shift register. Data is shifted at the falling edge of SCLK. Latch clock input for display data. When this pin is at a "H" level, the data is not latched to pass through the latch circuit. When the pin is at a "L" level, the data when the pin is at the "H" level is latched. -- Internal logic reset input upon power-on. During reset, the 18-bit internal latch, duty cycle register, digital register, LED register, and write/read address register are all reset, and the outputs of SEGA to SEGP(*a), D1 to D12 (*b), and LED1 to LED5 go off. Connecting of an external capacitor to the pin allows poweron reset. Input for oscillation circuit When an external resistor and a capacitor are connected, an oscillation circuit is formed. C=100pF, R=47kW fOSC=235kHz20%
POR
1
I
Schmitt with pull-up resistor using diode
OSC I OSC O
1 1
I O
--
SEGA-L SEGA-P D1-D12 D1-D16 LED1-LED5
12 *1 16 *2 12 2 16 *1 5
O O O
Anode side of Output for driving anode electrodes of VF display tube. VF display tube The output is complementary. Grid side of VF Output for driving grid electrodes of VF display tube. display tube LED The output is complementary. LED driving output. The output is complementary.
*a *b *1 *2
SEGA to SEGL in case of MSC7110-01 D1 to D16 in case of MSC7110-01 In case of MSC7110-01 In case of MSC7112-01
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Semiconductor
MSC7110-01/7112-01
ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage (1) Supply Voltage (2) Input Voltage Power Dissipation Storage Temperature Output Current Symbol VDD VDD-VEE VI PD TSTG IO1 IO2 IO3 Condition -- -- -- Ta25C -- All SEG output All DIGIT output LED1-LED5 Range -0.3 to +6.5 0 to 50 -0.3 to VDD+0.3 to 500 -55 to +150 -10 -60 -20 Unit V V V mW C mA mA mA
RECOMENDED OPERATING CONDITIONS
Parameter Supply Voltage (1) Supply Voltage (2) Oscillation Frequency Operating Temperature Symbol VDD VDD-VEE fOSC TOP Condition -- -- -- -- Range 4.5 to 5.5 25 to 45 200 to 500 -20 to +75 Unit V V kHz C
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD-VEE=45V, VDD=5V10%, Ta=-20 to +75C) Parameter High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current (1) Low Level Input Current (2) Symbol VIH VIL IIH IIL1 IIL2 Condition -- -- VDD=5.5V, VI=VDD VDD=5.5V, VI=0V VDD=5.5V, VI=0V VDD=4.5, IOH=-6mA VDD=4.5, IOL=0.2mA VDD=4.5, IOH=-30mA VDD=4.5, IOL=0.2mA VDD=4.5, IOH=-10mA VDD=4.5, IOL=0.1mA VDD=5.5V, No load fOSC=245kHz Min. 0.7VDD -- -- -- -27 VDD-2.2 -- VDD-2.9 -- VDD-1.5 -- -- Typ. -- -- -- -- -55 VDD-1.5 VEE+0.8 VDD-2.3 VEE+0.8 -- -- 8.5 Max. -- 0.3VDD 1 -1 -110 -- VEE+1.3 -- VEE+1.3 -- 0.5 15 Unit Applicable pin V V mA mA mA V V V V V V All input All input All input All input except POR POR All SEG output All SEG output All DIGIT output All DIGIT output LED1-LED5 LED1-LED5
High Level Output Voltage (1) VOH1 Low Level Output Voltage (1) VOL1 High Level Output Voltage (2) VOH2 Low Level Output Voltage (2) VOL2 High Level Output Voltage (3) VOH3 Low Level Output Voltage (3) VOL3 Current Consumption IDD
mA --
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Semiconductor AC Characteristics
MSC7110-01/7112-01
(VDD=5V10%, Ta=-20 to +75C) Parameter SCLK Cycle Time SCLK, LOAD Pulse Width Data Setup Time Data Hold Time SCLK-LOAD Time LOAD-SCLK Time LOAD Cycle Time 1* LOAD Cycle Time 2 Symbol tCP tW tDSU tDHD tSL tLS tLCYC1 tLCYC2 Condition -- -- -- -- -- -- fOSC=245kHz fOSC=245kHz Min. 2 1 500 500 2 2 205 200 Typ. -- -- -- -- -- -- -- -- Max. -- -- -- -- -- -- -- -- Unit ms ms ns ns ms ms ms ms
*
tLCYC1>16/fOSC must be satisfied.
tCP tW SCLK 0.7VDD tDSU DATA IN 0.7VDD 0.3VDD tDHD 0.7VDD tSL LOAD tW 0.7VDD 0.3VDD tLCYC2 tLCYC1 tLS 0.7VDD 0.7VDD 0.3VDD 0.3VDD
0.7VDD
Oscillation Characteristics
(VDD=5V, VDD-VEE=25V to 45V, Ta=-20 to +75C) Parameter Oscillation Frequency Symbol fOSC Condition C=100pF, R=47kW Min. 188 Typ. 235 Max. 282 Unit Applicable pin kHz OSCI, OSCO
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Semiconductor
MSC7110-01/7112-01
TIMING DIAGRAM
16-digit display
t1= 64 16 = 1024T D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 SEGn VDD VEE
60T
4T
t2 t3
VDD VEE
t1=Frame cycle t2=Display timing t3=Blank timing
fOSC=245kHz t1=4.096ms t2=240ms t3=16ms T=1/fOSC
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Semiconductor
Command Description
FUNCTION DESCRIPTION
Input data Command DATA DISPLAY Function The RAM data is output directly to the SEGA to SEGP pins (Positive logic) MSB b17 b16 b15 b14 b13 b12 b11 b10 *1 0 0
SEGP
b9
SEGJ
b8
SEGI
b7
b6
b5
SEGF
b4
SEGE
b3
SEGD
b2
SEGC
b1
SEGB
LSB b0
SEGA
*1
*1
*1
SEGK SEGH SEGG
SEGO SEGN SEGM SEGL
L.R LOAD
Display data is set in the LED register and output to the LED1 1 to LED5 pins (Positive logic) The number of digits is set in the digit register. The write address is set in the write address counter. (The write position is set.) The duty value is set in the duty cycle register. The TEST mode is set. 1
0 0
0 1
0

LED5 LED4 LED3 LED2 LED1
D.R LOAD W.A.C LOAD
23
22
21
20
1
1
0

23
22
21
20
D.C.R LOAD TEST LOAD MODE
1 1
1 0
1 1
1

23
22
21
20
MSC7110-01/7112-01
*1: Ignored in the case of MSC7110-01.
: Don't Care
12/18
Semiconductor Relation between write address and digit output
Write address count Corresponding digit output
MSC7110-01/7112-01
0 D1
1 D2
2 D3
3 D4
4 D5
5 D6
6 D7
7 D8
8
9
A
B
C
D
E
F
*1 *1 *1 *1 D9 D10 D11 D12 D13 D14 D15 D16
*1: Ignored in the case of MSC7112-01 Inputting Display Data LED display Display data is output to the LED1 to LED5 pins in correspondence with each bit by executing the L. RLOAD command. Input data uses positive logic. When the data is 1, the LED lights. When the data is 0, the LED goes off. VF display (RAM direct display) Set optional data in the digit register and the duty register, and execute the W.A.C LOAD command to set the display digit position. Execute the DATA DISPLAY command to write the b0 to b15 (*1) display data in the RAM. The write address counter is incremented by one. The write address counter counts sequentially 0, 1, 2,------, 14, 15, 0, 1, ----- regardless of the value of the digit register. *1 : b0 to b11 display data in the case of MSC7110-01. Brightness Adjustment The brightness can be adjusted by using the values of the duty cycle register (D.C.R) and the digit register (D.R). The value of the duty cycle register changes the pulse width (B) at the D1 to D16 output pins, and the value of the digit register changes the cycle (A). The table below gives the relation between the value of the duty cycle register and the duty. When all the values of the duty cycle register are 0 (in the case of 16-digit display), the display is blank.
D.C.R b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 B Dn A DUTY B/A -- 4/1024 8/1024 12/1024 0 0 0 0 D.C.R b3 b2 b1 b0 1 1 1 1 0 0 1 1 VDD VEE 0 1 0 1 DUTY B/A 16/1024 20/1024 24/1024 28/1024 1 1 1 1 D.C.R b3 b2 b1 b0 0 0 0 0 0 0 1 1 0 1 0 1 DUTY B/A 32/1024 36/1024 40/1024 44/1024 1 1 1 1 D.C.R b3 b2 b1 b0 1 1 1 1 0 0 1 1 0 1 0 1 DUTY B/A 48/1024 52/1024 56/1024 60/1024
A=64 n=64 16=1024 n : Number of display digits
13/18
Semiconductor Number of Display Digits
MSC7110-01/7112-01
The number of display digits is set by the digit register. The number of display digits ranges from 1 to 16 (*1). The value of the digit register and the number of digits are as follows:
D.R b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 Control digit *2 D1-D16 D1-D1 D1-D2 D1-D3 D.R b3 b2 b1 b0 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 Control digit D1-D4 D1-D5 D1-D6 D1-D7 D.R b3 b2 b1 b0 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 Control digit D1-D8 D1-D9 D1-D10 D1-D11 D.R b3 b2 b1 b0 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 Control digit D1-D12 *2 D1-D13 *2 D1-D14 *2 D1-D15
*1 1 to 12 digits in the case of the MSC7112-01 *2 Ignored in the case of the MSC7112-01
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Semiconductor
MSC7110-01/7112-01
APPLICATION CIRCUIT
MSC7110-01
Heater transformer VF display tube GRID (DIGIT)
Output port
VDD +5V
+ -
Microcontroller VSS
VDD SEG A-SEG L DATA IN SCLK MSC7110-01 LOAD VSS POR
+ -
ANODE (SEGMENT)
D1-D16 LED1 LED5 OSCO VEE R2 LED
OSCI C R
R2
-25 to -40V ZD
R1
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Semiconductor
MSC7110-01/7112-01
PACKAGE DIMENSIONS
(Unit : mm)
SDIP42-P-600-1.78
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 4.52 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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Semiconductor
MSC7110-01/7112-01
(Unit : mm) QFP44-P-910-0.80-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.35 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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Semiconductor
MSC7110-01/7112-01
(Unit : mm) QFP44-P-910-0.80-2K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.41 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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